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1 ltc1735-1 high efficiency synchronous step-down switching regulator the ltc ? 1735-1 is a synchronous step-down switching regulator controller optimized for cpu power. opti-loop compensation allows the transient response to be opti- mized over a wide range of output capacitance and esr values. the operating frequency (synchronizable up to 500khz) is set by an external capacitor allowing maximum flexibility in optimizing efficiency. the output voltage is monitored by a power good window comparator that indicates when the output is within 7.5% of its programmed value, con- forming to intel mobile cpu specifications. protection features include internal foldback current lim- iting, output overvoltage crowbar and optional short- circuit shutdown. soft-start is provided by an external capacitor that can be used to properly sequence supplies. the operating current level is user-programmable via an external current sense resistor. wide input supply range allows operation from 3.5v to 30v (36v maximum). pin defeatable burst mode tm operation provides high efficiency at low load currents while 99% duty cycle provides low dropout operation. n dual n-channel mosfet synchronous drive n programmable/synchronizable fixed frequency n v out range: 0.8v to 7v n wide v in range: 3.5v to 36v operation n very low dropout operation: 99% duty cycle n opti-loop tm compensation minimizes c out n 1% output voltage accuracy n power good output voltage monitor n internal current foldback n output overvoltage crowbar protection n latched short-circuit shutdown timer with defeat option n optional programmable soft-start n remote output voltage sense n logic controlled micropower shutdown: i q < 25 m a n available in 16-lead narrow ssop and so packages figure 1. cpu core dc/dc converter with dynamic voltage selection from speedstep enabled processors , ltc and lt are registered trademarks of linear technology corporation. burst mode and opti-loop are trademarks of linear technology corporation. pentium is a registered trademark of intel corporation. speedstep is a trademark of intel corporation. n notebook and palmtop computers, pdas n power supply for mobile pentium ? iii processor with speedstep tm technology n cellular telephones and wireless modems 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c osc run/ss i th pgood sense sense + v osense sgnd tg boost sw v in intv cc bg pgnd extv cc ltc1735-1 1000pf c c2 330pf c osc 47pf 47pf c c1 47pf c ss 0.1 f r c1 33k + 4.7 f 5v (optional) 47pf q4 2n7002 gnd 47pf r1 10k 0.5% c in : marcon thcr70e1h226zt c out : panasonic eefue06181r l1: panasonic etqp6rz1r20hfa r sense : irc crf2010-01-r004j v out 1.35v to 1.60v 12a v sel = 1: v out = 1.60v v sel = 0: v out = 1.35v d1 cmdsh-3 d2 mbrs340t3 c b 0.22 f q1 fds6680a c in 22 f 50v ceramic 2 l1 1.2 h r sense 0.004 v in 4.5v to 24v pgood q2, q3 fds6680a 2 10 1735-1 f01 r3 33.2k 1% r2 14.3k 0.5% 10 + c out 180 f 4v panasonic sp 4 descriptio u features applicatio s u typical applicatio u
2 ltc1735-1 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) input supply voltage (v in )........................ 36v to C 0.3v topside driver supply voltage (boost)... 42v to C 0.3v switch voltage (sw) ................................... 36v to C 5v intv cc , extv cc (boost, sw) voltages ..... 7v to C 0.3v sense + , sense C , pgood voltages ................ 1.1(intv cc + 0.3v) to C 0.3v i th , v osense , c osc voltages .....................2.7v to C 0.3v run/ss voltage ....................(intv cc + 0.3v) to C 0.3v peak driver output current <10 m s (tg, bg) .............. 3a intv cc output current ......................................... 50ma operating ambient temperature range ltc1735c-1 ............................................ 0 c to 85 c ltc1735i-1 ........................................ C 40 c to 85 c junction temperature (note 2) ............................. 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c electrical characteristics order part number ltc1735cgn-1 ltc1735cs-1 ltc1735ign-1 ltc1735is-1 consult factory for military grade parts. t jmax = 125 c, q ja = 130 c/w (gn) t jmax = 125 c, q ja = 110 c/w (s) top view s package 16-lead plastic so gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c osc run/ss i th pgood sense sense + v osense sgnd tg boost sw v in intv cc bg pgnd extv cc the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units main control loop i vosense feedback current (note 3) C 4 C 25 na v osense feedback voltage (note 3) l 0.792 0.8 0.808 v d v linereg reference voltage line regulation v in = 3.6v to 30v (note 3) 0.001 0.02 %/v d v loadreg output voltage load regulation (note 3) measured in servo loop; v ith = 0.7v l 0.1 0.3 % measured in servo loop; v ith = 2v l C 0.1 C 0.3 % df max maximum duty factor in dropout 98 99.4 % g m transconductance amplifier g m 1.3 mmho v ovl feedback overvoltage lockout l 0.84 0.86 0.88 v i q input dc supply current (note 5) normal mode 3.6v < v in < 30v 450 m a shutdown v run/ss = 0v 15 25 m a v run/ss run pin start threshold v run/ss , ramping positive 1.0 1.5 1.9 v run pin begin latchoff threshold v run/ss , ramping positive 4.1 4.5 v i run/ss soft-start charge current v run/ss = 0v C 0.7 C 1.2 m a i scl run/ss discharge current soft short condition, v osense = 0.5v, 0.5 2 4 m a v run/ss = 4.5v uvlo undervoltage lockout measured at v in pin (ramping negative) l 3.5 3.9 v d v sense(max) maximum current sense threshold v osense = 0.7v l 60 75 85 mv i sense sense pins total source current v sense C = v sense + = 0v 60 80 m a t on(min) minimum on-time tested with a square wave (note 4) 160 200 ns gn part marking 17351 1735i1
3 ltc1735-1 note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc1735cs-1, ltc1735is-1: t j = t a + (p d ? 110 c/w) ltc1735cgn-1, ltc1735ign-1: t j = t a + (p d ? 130 c/w) note 3: the ltc1735-1 is tested in a feedback loop that servos v osense to the balance point for the error amplifier (v ith = 1.2v). note 4: the minimum on-time condition corresponds to an inductor peak-to-peak ripple current > 40% of i max (see minimum on-time considerations in the applications information section). note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: oscillator frequency is tested by measuring the c osc charge current (i osc ) and applying the formula: f khz cpf i i osc osc chg dis () .() () = + ? ? ? ? + ? ? ? ? 8 477 10 11 11 8 1 note 7: rise and fall times are measured using 10% to 90% levels. delay times are measured using 50% levels. electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 15v, v run/ss = 5v unless otherwise noted. symbol parameter conditions min typ max units tg transition time: (note 7) tg t r rise time c load = 3300pf 50 90 ns tg t f fall time c load = 3300pf 50 90 ns bg transition time: (note 7) bg t r rise time c load = 3300pf 50 90 ns bg t f fall time c load = 3300pf 40 80 ns tg/bg t1d top gate off to synchronous c load = 3300pf each driver 100 ns gate-on delay time tg/bg t2d synchronous gate off to top c load = 3300pf each driver 70 ns gate-on delay time internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v, v extvcc = 4v 5.0 5.2 5.4 v v ldo(int) intv cc load regulation i cc = 0ma to 20ma, v extvcc = 4v 0.2 1 % v ldo(ext) extv cc drop voltage i cc = 20ma, v extvcc = 5v 130 200 mv v extvcc extv cc switchover voltage i cc = 20ma, extv cc ramping positive l 4.5 4.7 v v extvcc(hys) extv cc hysteresis 0.2 v oscillator f osc oscillator frequency (note 6), c osc = 43pf 265 300 335 khz f h /f osc maximum sync frequency ratio 1.3 pgood pin v pg(sync) pgood threshold for sync ramping negative 0.9 1.2 v v pg(fc) pgood threshold for force cont. 0.76 0.8 0.84 v v pgl pgood voltage low i pgood = 2ma 110 200 mv i pgood pgood pull-up current v pgood = 0.85v C 0.17 m a v pg pgood trip level v osense with respect to set output voltage v osense ramping negative C 6.0 C7.5 C9.5 % v osense ramping positive 6.0 7.5 9.5 %
4 ltc1735-1 typical perfor a ce characteristics uw efficiency vs load current (3 operating modes) load current (a) 0.001 efficiency (%) 60 70 80 burst sync cont 10 1735-1 g01 50 40 20 0.01 0.1 1 30 100 90 v in = 10v v out = 3.3v r s = 0.01 f o = 300khz extv cc open efficiency vs load current load current (a) 10ma 100ma 1a 10a efficiency (%) 1735-1 g02 100 90 80 70 60 50 40 v in = 5v extv cc = 5v v out = 1.6v v in = 24v v in = 15v input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1735-1 g03 25 30 95 extv cc = 5v v out = 1.6v figure 1 i out = 5a i out = 0.5a efficiency vs input voltage v in C v out dropout voltage vs load current load regulation efficiency vs input voltage input voltage (v) 0 70 efficiency (%) 75 80 85 90 100 5 10 15 20 1735-1 g04 25 30 95 extv cc open v out = 1.6v figure 1 i out = 5a i out = 0.5a load current (a) 0 normalized v out (%) 0.2 0.1 8 1735-1 g05 0.3 0.4 2 4 6 10 0 fcb = 0v v in = 15v figure 1 load current (a) 0 0 v in ?v out (mv) 500 400 300 200 100 2468 1735-1 g06 10 r sense = 0.005 v out = 5v ?5% drop input and shutdown currents vs input voltage input voltage (v) 05 0 input current ( a) shutdown current ( a) 200 500 10 20 25 1735-1 g07 100 400 300 0 40 100 20 80 60 15 30 35 extv cc open shutdown extv cc = 5v intv cc line regulation extv cc switch drop vs intv cc load current input voltage (v) 0 intv cc voltage (v) 4 5 6 15 25 1735-1 g08 3 2 510 20 30 35 1 0 1ma load intv cc load current (ma) 0 extv cc ?intv cc (mv) 300 400 500 40 1735-1 g09 200 100 0 10 20 30 50
5 ltc1735-1 typical perfor a ce characteristics uw maximum current sense threshold vs normalized output voltage (foldback) maximum current sense threshold vs v run/ss maximum current sense threshold vs sense common mode voltage normalized output voltage (%) 0 maximum current sense threshold (mv) 40 50 60 100 1735-1 g10 30 20 0 25 50 75 10 80 70 v run/ss (v) 0 0 maximum current sense threshold (mv) 20 40 60 80 1234 1735-1 g11 56 v sense(cm) = 1.6v common mode voltage (v) 0 maximum current sense threshold (mv) 72 76 80 4 1735-1 g12 68 64 60 1 2 3 5 maximum current sense voltage vs i th voltage v ith (v) 0 maximum current sense voltage (v) 30 50 70 90 2 1735-1 g13 10 ?0 20 40 60 80 0 ?0 ?0 0.5 1 1.5 2.5 output current vs duty cycle duty cycle (%) 0 0 average output current i out /i max (%) 20 40 60 80 100 20 40 60 80 1735-1 g14 100 f sync = f o i out /i max (synchronized) i out /i max (free run) v ith vs v run/ss v run/ss (v) 0 0 v ith (v) 0.5 1.0 1.5 2.0 2.5 1 234 1735-1 g15 56 v osense = 0.7v sense pins total source current v sense common mode voltage (v) 0 i sense ( a) 0 1735-1 g16 ?0 100 24 50 100 6 i th voltage vs load current load current (a) 0 0 i th voltage (v) 0.5 1.0 1.5 2.0 2.5 1 234 1735-1 g17 56 v in = 10v v out = 3.3v r sense = 0.01 f o = 300khz continuous mode burst mode operation synchronized f = f o maximum current sense threshold vs temperature temperature ( c) ?0 60 maximum current sense threshold (mv) 65 70 75 80 ?5 10 35 60 1735-1 g18 85 110 135 v sense(cm) = 1.6v
6 ltc1735-1 typical perfor a ce characteristics uw oscillator frequency vs temperature temperature ( c) ?0 ?5 250 frequency (khz) 270 300 10 60 85 1735-1 g19 260 290 280 35 110 135 c osc = 47pf run/ss pin current vs temperature temperature ( c) 40 ?5 ? run/ss current ( a) ? 0 10 60 85 1735-1 g20 ? ? ? 35 110 135 v run/ss = 0v pgood pin current vs temperature temperature ( c) 40 ?5 ?.0 pgood pin current ( a) 0.6 0 10 60 85 1735-1 g21 0.8 0.2 0.4 35 110 135 v pgood = 0.85v start-up v out 1v/div v run/ss 5v/div i l 5a/div v in = 15v 5ms/div 1735-1 g22 v out = 1.6v r load = 0.16 w v out(ripple) (synchronized) v out 10mv/div i l 5a/div ext sync f = f o 10 m s/div 1735-1 g23 v in = 15v v out = 1.6v figure 1 v out(ripple) (burst mode operation) v out 20mv/div i l 5a/div v in = 15v 50 m s/div 1735-1 g24 v out = 1.6v figure 1 v out(ripple) (burst mode operation) v out 20mv/div i l 5a/div v in = 15v 5 m s/div 1735-1 g25 v out = 1.6v load step (burst mode operation) v out 50mv/div i l 5a/div 10ma to 10 m s/div 1735-1 g26 11a load step v in = 15v v out = 1.6v load step (continuous mode) v out 50mv/div i l 5a/div 0a to 10 m s/div 1735-1 g27 11a load step pgood = 0v v in = 15v v out = 1.6v figure 1 figure 1 figure 1 i load = 10ma i load = 50ma i load = 1.5a
7 ltc1735-1 c osc (pin 1): external capacitor c osc from this pin to ground sets the operating frequency. run/ss (pin 2): combination of soft-start and run control inputs. a capacitor to ground at this pin sets the ramp time to full current output. the time is approximately 1.25s/ m f. forcing this pin below 1.5v causes the device to be shut down. in shutdown all functions are disabled. latchoff overcurrent protection is also invoked via this pin as described in the applications information section. i th (pin 3): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 2.4v. pgood (pin 4): open-drain logic output and forced continuous/synchronization input. the pgood pin is pulled to ground when the voltage on the v osense pin is not within 7.5% of its nominal set point. if power good indication is not needed, this pin can be tied to ground to force continuous synchronous operation. clocking this pin with a signal above 1.5v p-p synchronizes the internal oscillator to the external clock. synchronization only occurs while the main output is in regulation (pgood not internally pulled low). when synchronized, burst mode operation is disabled but cycle skipping is allowed at low load currents. this pin requires a pull-up resistor for power good indication. do not connect this pin directly to an external source (or intv cc ). do not exceed intv cc on this pin. sense C (pin 5): the (C) input to the current comparator. sense + (pin 6): the (+) input to the current comparator. built-in offsets between sense + and sense C pins in conjunction with r sense set the inductor current trip threshold. v osense (pin 7): receives the feedback voltage from an external resistive divider across the output. sgnd (pin 8): small-signal ground. all small-signal components such as c osc , c ss , the feedback divider plus the loop compensation resistors and capacitor(s) should single-point tie to this pin. this pin should, in turn, connect to pgnd. extv cc (pin 9): input to the internal switch connected to intv cc . this switch closes and supplies v cc power when- ever extv cc is higher than 4.7v. see extv cc connection in applications information section. do not exceed 7v on this pin and ensure extv cc is v in . pgnd (pin 10): driver power ground. this pin connects to the source of the bottom n-channel mosfet, the anode of the schottky diode and the (C) terminal of c in . bg (pin 11): high current gate drive for the bottom n-channel mosfet. voltage swing at this pin is from ground to intv cc . intv cc (pin 12): output of the internal 5.2v low dropout regulator and extv cc switch. the driver and control circuits are powered from this voltage. decouple to power ground with a 1 m f ceramic capacitor placed directly adja- cent to the ic together with a minimum of 4.7 m f tantalum or other low esr capacitor. v in (pin 13): main supply pin. this pin must be closely decoupled to power ground. sw (pin 14): switch node connection to inductor and bootstrap capacitor. voltage swing at this pin is from a schottky diode (external) voltage drop below ground to v in . boost (pin 15): supply to topside floating driver. the bootstrap capacitor is returned to this pin. voltage swing at this pin is from a diode drop below intv cc to v in + intv cc . tg (pin 16): high current gate drive for top n-channel mosfet. this is the output of a floating driver with a voltage swing equal to intv cc superimposed on the switch node voltage sw. pi fu ctio s uuu
8 ltc1735-1 operatio u (refer to functional diagram) fu ctio al diagra uu w sw + + 0.86v + 0.55v 2.4v 0.8v 0.86v i 1 + i 2 + ea a burst disable fc ov g m =1.3m b + 4.8v irev + + f fc intv cc s r q drop out det 0.8v ref switch logic sd 6v r1 run/ss c ss r c v osense v fb 1.2 a run soft- start + over- current latchoff sd i th c c 0.17 a osc 4(v fb ) buffered i th slope comp + + 3mv icmp r2 2k 45k bot top on force bot 45k 100k intv cc 30k 30k sense + sense sync 1.2v + 0.74v 0.8v c top uvl bot intv cc 5.2v ldo reg v in + c intvcc + intv cc bg pgnd v in v in boost tg intv cc c b d b d 1 l v out r sense c out c osc + c in extv cc sgnd c osc 1735-1 fd 1 pgood 4 8 13 15 16 14 12 11 10 9 5 6 3 2 7 main control loop : the ltc1735-1 uses a constant frequency, current mode step-down architecture. during normal operation, the top mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the main current comparator i 1 resets the rs latch. the peak inductor current at which i 1 resets the rs latch is controlled by the voltage on pin i th , which is the output of error amplifier ea. pin v osense , described in the pin functions, allows ea to receive an output feedback voltage v fb from the external resistive divider. when the load current increases, it causes a slight decrease in v fb relative to the 0.8v refer- ence, which in turn causes the i th voltage to increase until the average inductor current matches the new load cur- rent. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current comparator i 2 , or the beginning of the next cycle. the top mosfet driver is powered from a floating boot- strap capacitor c b . this capacitor is normally recharged from intv cc through an external schottky diode when the top mosfet is turned off. as v in decreases towards v out , the converter will attempt to turn on the top mosfet con- tinuously (dropout). a dropout counter detects this con- dition and forces the top mosfet to turn off for about 500ns every tenth cycle to recharge the bootstrap capacitor.
9 ltc1735-1 operatio u (refer to functional diagram) the main control loop is shut down by pulling pin 2 (run/ ss) low. releasing run/ss allows an internal 1.2 m a current source to charge soft-start capacitor c ss . when c ss reaches 1.5v, the main control loop is enabled with the i th voltage clamped at approximately 30% of its maximum value. as c ss continues to charge, i th is gradually re- leased allowing normal operation to resume. if v out has not reached 70% of its final value when c ss has charged to 4.1v, latchoff can be invoked as described in the applications information section. the internal oscillator can be synchronized to an external clock applied though a series resistor to the pgood pin and can lock to a frequency between 90% and 130% of its nominal rate set by capacitor c osc . an overvoltage comparator ov guards against transient overshoots (> 7.5%) as well as other more serious conditions that may overvoltage the output. in this case, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. foldback current limiting for an output shorted to ground is provided by amplifier a. as v osense drops below 0.6v, the buffered i th input to the current comparator is gradually pulled down to a 0.86v clamp. this reduces peak inductor current to about 1/4 of its maximum value. low current operation the ltc1735-1 has three low current modes controlled by the pgood pin. burst mode operation is selected when the pgood pin is above 0.8v (typically tied through a resistor to intv cc ). during burst mode operation, if the error amplifier drives the i th voltage below 0.86v, the buffered i th input to the current comparator will be clamped at 0.86v. the inductor current peak is then held at approximately 20mv/r sense (about 1/4 of maximum output current). if i th then drops below 0.5v, the burst mode comparator b will turn off both mosfets to maxi- mize efficiency. the load current will be supplied solely by the output capacitor until i th rises above the 60mv hysteresis of the comparator and switching is resumed. burst mode operation is disabled by comparator f when the pgood pin is brought below 0.8v. this forces continuous operation and assists in controlling voltage regulation. if the output voltage is not within 7.5% of its nominal value the pgood open-drain output will be pulled low and burst mode operation will be disabled. foldback current, short-circuit detection and short-circuit latchoff the run/ss capacitor, c ss , is used initially to limit the inrush current of the switching regulator. after the con- troller has been started and been given adequate time to charge up the output capacitors and provide full load current, c ss is used as a short-circuit time-out circuit. if the output voltage falls to less than 70% of its nominal output voltage, c ss begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. if the condition lasts for a long enough period as determined by the size of the c ss , the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overridden by providing a current >5 m a at a compliance of 5v to the run/ss pin. this current shortens the soft-start period but also prevents net discharge of c ss during an overcurrent and/or short- circuit condition. foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. intv cc /extv cc power power for the top and bottom mosfet drivers and most of the internal circuitry of the ltc1735-1 is derived from the intv cc pin. when the extv cc pin is left open, an internal 5.2v low dropout regulator supplies the intv cc power from v in . if extv cc is raised above 4.7v, the internal regulator is turned off and an internal switch connects extv cc to intv cc . this allows a high efficiency source, such as the primary or a secondary output of the converter itself, to provide the intv cc power. voltages up to 7v can be applied to extv cc for additional gate drive capability. to provide clean start-up and to protect the mosfets, undervoltage lockout is used to keep both mosfets off until the input voltage is above 3.5v.
10 ltc1735-1 operatio u (refer to functional diagram) power good a window comparator monitors the output voltage and its open-drain output is pulled low when the divided down output voltage (appearing at the v osense pin) is not within 7.5% of the reference voltage of 0.8v. during a programmed output voltage transition (i.e., a transition from 1.55v to 1.3v) the pgood open-drain output will be pulled low and burst mode operation will be disabled until the output voltage is within 7.5% of its newly programmed value. when the pgood pin is driven by an external oscillator through a series resistor, cycle-skipping operation is invoked and the internal oscillator is synchronized to the external clock by comparator c. in this mode, the 25% minimum inductor current clamp is removed, providing low noise, constant frequency discontinuous operation over the widest possible output current range. this con- stant frequency operation is not quite as efficient as burst mode operation, but does provide a lower noise, constant frequency operation. when the power good window com- parator indicates the output is not in regulation, the pgood pin is pulled to ground and synchronization is inhibited. obviously when driving the pgood pin with an external clock the power good indication is not available unless additional circuitry is added. if the pgood pin is tied to ground, continuous operation is forced. this operation is the least efficient mode, but is desirable in certain applications. the output can source or sink current in this mode. when forcing continuous operation and sinking current, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levelsbeware. applicatio s i for atio wu u u the basic ltc1735-1 application circuit is shown in figure 1 on the first page of this data sheet. external component selection is driven by the load requirement and begins with the selection of r sense . once r sense is known, c osc and l can be chosen. next, the power mosfets and d1 are selected. the operating frequency and the inductor are chosen based largely on the desired amount of ripple current. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specifications. the circuit shown in figure 1 can be configured for operation up to an input voltage of 28v (limited by the external mosfets). r sense selection for output current r sense is chosen based on the required output current. the ltc1735-1 current comparator has a maximum threshold of 75mv/r sense and an input common mode range of sgnd to 1.1(intv cc ). the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, d i l . allowing a margin for variations in the ltc1735-1 and external component values yields: r mv i sense max = 50 c osc selection for operating frequency and synchronization the choice of operating frequency and inductor value is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses, both gate charge loss and transition loss. however, lower frequency operation requires more inductance for a given amount of ripple current. the ltc1735-1 uses a constant frequency architecture with the frequency determined by an external oscillator capacitor c osc . each time the topside mosfet turns on, the voltage on c osc is reset to ground. during the on-time, c osc is charged by a fixed current. when the voltage on the capacitor reaches 1.19v, c osc is reset to ground. the process then repeats.
11 ltc1735-1 applicatio s i for atio wu u u the value of c osc is calculated from the desired operating frequency assuming no external clock input on the pgood pin: cpf frequency osc () .( ) = ? ? 16110 11 7 a graph for selecting c osc versus frequency is given in figure 2. the maximum recommended switching fre- quency is 550khz . the internal oscillator runs at its nominal frequency (f o ) when the pgood pin is pulled high (to intv cc ) though a series resistor or connected to ground. clocking the pgood pin above and below 1.2v will cause the internal oscillator to injection-lock to an external clock signal applied to the pgood pin with a frequency between 0.9f o and 1.3f o . the clock high level must exceed 1.3v for at least 0.3 m s, and the clock low level must be less than 0.3v for at least 0.3 m s. the top mosfet turn-on will synchro- nize with the rising edge of the external clock. attempting to synchronize to too high of an external frequency (above 1.3f o ) can result in inadequate slope compensation and possible loop instability at high duty cycles. if this condition exists, simply lower the value of c osc so (f ext = f o ) according to figure 2. clamp present in burst mode operation is removed, providing constant frequency discontinuous operation over the widest possible output current range. in this mode the synchronous mosfet is forced on once every 10 clock cycles to recharge the bootstrap capacitor. this minimizes audible noise while maintaining reasonably high efficiency. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge losses. in addition to this basic trade off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current d i l decreases with higher induc- tance or frequency and increases with higher v in or v out : d i fl v v v l out out in = ? ? 1 1 ()( ) accepting larger values of d i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is d i l = 0.3 to 0.4(i max ). remember, the maximum d i l occurs at the maximum input voltage. the inductor value also has an effect on low current operation. the transition to low current operation begins when the inductor current reaches zero while the bottom mosfet is on. burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher d i l ) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. figure 2. timing capacitor value operating frequency (khz) 0 100 200 300 400 500 600 c osc value (pf) 1735-1 f02 100.0 87.5 75.0 62.5 50.0 37.5 25.0 12.5 0 when synchronized to an external clock, burst mode operation is disabled but the inductor current is not allowed to reverse. the 25% minimum inductor current
12 ltc1735-1 applicatio s i for atio wu u u inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manufacturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. because they generally lack a bobbin, mounting is more difficult. however, designs for surface mount are available that do not increase the height significantly. power mosfet and d1 selection two external power mosfets must be selected for use with the ltc1735-1: an n-channel mosfet for the top (main) switch, and an n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak gate drive levels are set by the intv cc voltage. this voltage is typically 5.2v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most ltc1735-1 applications. the only exception is when low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specification for the mosfets as well; most of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage and maximum output current. when the ltc1735-1 is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switch duty cycle vv v out in in out in = = the mosfet power dissipations at maximum output current are given by: p v v ir kv i c f p vv v ir main out in max ds on in max rss sync in out in max ds on = () + () + ()( )( )() = () + () 2 2 2 1 1 d d () () where d is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transi- tion losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100%. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet characteristics. the constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. the schottky diode d1 shown in figure 1 conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom kool m m is a registered trademark of magnetics, inc.
13 ltc1735-1 applicatio s i for atio wu u u mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. a 3a schottky is generally a good size for 10a to 12a regu- lators due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. the diode may be omitted if the efficiency loss can be tolerated. c in selection in continuous mode, the source current of the top n-channel mosfet is a square wave of duty cycle v out / v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ii v v v v rms o max out in in out @ ? ? ? ? () / 1 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. c out selection the selection of c out is primarily determined by the effective series resistance (esr) to minimize voltage ripple. the output ripple ( d v out ) in continuous mode is deter- mined by: dd v i esr fc out l out ?+ ? ? ? ? 1 8 where f = operating frequency, c out = output capacitance, and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. typically, once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. with d i l = 0.3i out(max) and allowing for 2/3 of the ripple due to esr, the output ripple will be less than 50mv at max v in assuming: c out required esr < 2.2 r sense c out > 1/(8fr sense ) the first condition relates to the ripple current into the esr of the output capacitance while the second term guaran- tees that the output voltage does not significantly dis- charge during the operating frequency period due to ripple current. the choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. the i th pin opti-loop compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. the selection of output capacitors for cpu or other appli- cations with large load current transients is primarily de- termined by the voltage tolerance specifications of the load. the resistive component of the capacitor, esr, multiplied by the load current change plus any output voltage ripple must be within the voltage tolerance of the load (cpu). the required esr due to a load current step is: r esr < d v/ d i where d i is the change in current from full load to zero load (or minimum load) and d v is the allowed voltage deviation (not including any droop due to finite capacitance). the amount of capacitance needed is determined by the maximum energy stored in the inductor. the capacitance must be sufficient to absorb the change in inductor current when a high current to low current transition occurs. the opposite load current transition is generally determined by the control loop opti-loop components, so make sure not to over compensate and slow down the response. the minimum capacitance to assure the inductors energy is adequately absorbed is: c li vv out out > d () d () 2 2 where d i is the change in load current.
14 ltc1735-1 applicatio s i for atio wu u u manufacturers such as nichicon, united chemicon and sanyo can be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications, multiple capacitors may need to be used in parallel to meet the esr, rms current handling and load step requirements of the application. aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. special polymer surface mount capacitors offer very low esr but have much lower capacitive density per unit volume than other capacitor types. these capacitors offer a very cost- effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long-term reliability. a typical application will require several to many aluminum electrolytic capacitors in parallel. a combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. other capacitor types include sanyo os-con, nichicon pl series and sprague 595d series. consult manufacturers for other specific recommendations. intv cc regulator an internal p-channel low dropout regulator produces the 5.2v supply that powers the drivers and internal circuitry within the ltc1735-1. the intv cc pin can supply a maximum rms current of 50ma and must be bypassed to ground with a minimum of 4.7 m f tantalum, 10 m f special polymer or low esr type electrolytic capacitor. a 1 m f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is required to supply the high transient cur- rents required by the mosfet gate drivers. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc1735-1 to be exceeded. the system supply current is normally domi- nated by the gate charge current. additional loading of intv cc also needs to be taken into account for the power dissipation calculations. the total intv cc current can be supplied by either the 5.2v internal linear regulator or by the extv cc input pin. when the voltage applied to the extv cc pin is less than 4.7v, all of the intv cc current is supplied by the internal 5.2v linear regulator. power dissipation for the ic in this case is highest, (v in )(i intvcc ), and overall efficiency is lowered. the gate charge current is dependant on operating frequency as discussed in the efficiency consideration section. the junction tempera- ture can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the ltc1735cs-1 is limited to less than 17ma from a 30v supply when not using the extv cc pin as follows: t j = 70 c + (17ma)(30v)(110 c/w) = 126 c use of the extv cc input pin reduces the junction tempera- ture to: t j = 70 c + (17ma)(5v)(110 c/w) = 79 c to prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum v in . extv cc connection the ltc1735-1 contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. whenever the extv cc pin is above 4.7v the internal 5.2v regulator shuts off, the switch closes and intv cc power is supplied via extv cc until extv cc drops below 4.5v. this allows the mosfet gate drive and control power to be derived from the output or other external source during normal operation. when the output is out of regulation (start-up, short circuit) power is supplied from the internal regulator. do not apply greater than 7v to the extv cc pin and ensure that extv cc < v in .
15 ltc1735-1 applicatio s i for atio wu u u significant efficiency gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(efficiency). for 5v regulators this simply means connecting the extv cc pin directly to v out . however, for dynamic (vid-like) programmed regulators and other lower voltage regulators, additional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc: 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5.2v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v to 7v output regulator and provides the highest efficiency. for output voltages > 5v, extv cc is required to connect to v out so the sense pins absolute maximum ratings are not exceeded. 3. extv cc connected to an external supply (this option is the most likely used). if an external supply is available in the 5v to 7v range, such as notebook main 5v system power, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. this is the typical case as the 5v power is almost always present and is derived by another high efficiency regulator. 4. extv cc connected to an output-derived boost net- work. for low output voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with either the inductive boost winding or capacitive charge pump circuits. refer to the ltc1735 data sheet for details. the charge pump has the advantage of simple magnetics. output voltage programming the output voltage is set by an external resistive divider according to the following formula: vv r r out =+ ? ? ? ? 08 1 2 1 . the resistive divider is connected to the output as shown in figure 3 allowing remote voltage sensing. the output voltage can be digitally set to voltages between any two levels with the addition of a resistor and small signal n-channel mosfet as shown in the circuit of figure 1. dynamic output voltage selection can be accom- plished with this technique. output voltages of 1.30v and 1.55v are set by the resistors r1 to r3. with the gate of the mosfet low, (v g = 0), the output voltage is set by the ratio of r1 to r2. when the mosfet is on (v g = high), the output voltage is the ratio of r1 to the parallel combina- tion of r2 and r3. with the available power good output (pgood), the circuit in figure 1 creates a low cost intel pentium iii mobile processor compliant supply. the ltc1735-1 has remote sense capability. the top of the internal resistive divider is connected to v osense and is referenced to the sgnd pin. this allows a kelvin connec- tion for remotely sensing the output voltage directly across the load, eliminating any pc board trace resistance errors. topside mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. note that the voltage across c b is about a diode drop below intv cc . when the topside mosfet is to be turned on, the driver places the c b voltage across the gate-source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage sw rises to v in and the boost pin rises to v in + intv cc . the value of the boost capacitor c b needs to be 100 times greater than the total input capacitance of the topside mosfet. in most applications 0.1 m f to 0.33 m f is adequate. the reverse breakdown on d b must be greater than v in(max) . figure 3. setting the ltc1735-1 output voltage v osense v out r2 1735-1 f03 ltc1735-1 r1 47pf sgnd
16 ltc1735-1 applicatio s i for atio wu u u when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if you make a change and the input current decreases, then you improved the efficiency. if there is no change in input current, then there is no change in efficiency. sense + / sense C pins the common mode input range of the current comparator is from 0v to 1.1(intv cc ). continuous linear operation is guaranteed throughout this range allowing output volt- ages anywhere from 0.8v to 7v. a differential npn input stage is used and is biased with internal resistors from an internal 2.4v source as shown in the functional diagram. this causes current either to be sourced or sunk by these pins depending on the output voltage. if the output voltage is below 2.4v, current will flow out of both sense pins to the main output. this forces a minimum load current that can be fulfilled by the v out resistive divider. the maxi- mum current flowing out of the sense pins is: i sense + + i sense C = (2.4v C v out )/24k since v osense is servoed to the 0.8v reference voltage, we can choose r1 in figure 3 to have a maximum value to absorb this current: r max k v vv out 124 08 24 () . . = ? ? ? ? regulating an output voltage of 1.8v, the maximum value of r1 should be 32k. note that for output voltages above 2.4v no maximum value of r1 is necessary to absorb the sense currents; however, r1 is still bounded by the v osense feedback current. soft-start/run function the run/ss pin is a multipurpose pin that provides a soft- start function and a means to shut down the ltc1735-1. soft-start reduces surge currents from v in by gradually increasing the controllers current limit i th(max) . this pin can also be used for power supply sequencing. pulling the run/ss pin below 1.5v puts the ltc1735-1 into a low quiescent current shutdown (i q < 25 m a). this pin can be driven directly from logic as shown in figures 4 and 5. releasing the run/ss pin allows an internal 1.2 m a current source to charge up the external soft-start capacitor c ss. if run/ss has been pulled all the way to ground there is a delay before starting of approximately: t v a csfc delay ss ss = m =m () 15 12 125 . . ./ when the voltage on run/ss reaches 1.5v the ltc1735-1 begins operating with a current limit at ap- proximately 25mv/r sense . as the voltage on run/ss increases from 1.5v to 3v, the internal current limit is increased from 25mv/r sense to 75mv/r sense . the out- put current limit ramps up slowly, taking an additional 1.25s/ m f to reach full current. ramping the output cur- rent slowly reduces the starting surge current required from the input supply. diode d1 in figure 4 and figure 5 reduces the start delay while allowing c ss to charge up slowly for the soft-start function. this diode and c ss can be deleted if soft-start is not needed. the run/ss pin has an internal 6v zener clamp (see functional diagram). figure 5. run/ss pin interfacing with latchoff defeated figure 4. run/ss pin interfacing 3.3v or 5v run/ss run/ss d1 c ss c ss 1735-1 f04 3.3v or 5v run/ss v in intv cc run/ss d1 d1 c ss r ss c ss r ss 1735-1 f05 (a) (b) fault conditions: overcurrent latchoff the run/ss pin also provides the ability to shut off the controller and latchoff when an overcurrent condition is detected. the run/ss capacitor c ss is used initially to turn on and limit the inrush current of the controller. after the controller has been started and given adequate time to charge up the output capacitor and provide full load
17 ltc1735-1 applicatio s i for atio wu u u current, c ss is used as a short-circuit timer. if the output voltage falls to less than 70% of its nominal output voltage after c ss reaches 4.1v, the assumption is made that the output is in a severe overcurrent and/or short-circuit condition and c ss begins discharging. if the condition lasts for a long enough period as determined by the size of c ss , the controller will be shut down until the run/ss pin voltage is recycled. this built-in latchoff can be overridden by providing a current > 5 m a at a compliance of 5v to the run/ss pin as shown in figure 5a. this current shortens the soft-start period but also prevents net discharge of the run/ss capacitor during a severe overcurrent and/or short-circuit conditions. when deriving the 5 m a current from v in as in figure 5a, current latchoff is always defeated. the diode connecting this pull-up resistor to intv cc , as in figure 5b, eliminates any extra supply current during shutdown while eliminating the intv cc loading from preventing controller start-up. if the voltage on c ss does not exceed 4.1v, the overcurrent latch is not armed and the function is disabled. why should you defeat current latchoff? during the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. defeating this feature will easily allow trouble- shooting of the circuit and pc layout. the internal short circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. after the design is complete, a decision can be made whether to enable the latchoff feature. the value of the soft-start capacitor c ss will need to be scaled with output current, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out ) (10 C4 ) (r sense ) the minimum recommended soft-start capacitor of c ss = 0.1 m f will be sufficient for most applications. fault conditions: current limit and current foldback the ltc1735-1 current comparator has a maximum sense voltage of 75mv resulting in a maximum mosfet current of 75mv/r sense . the ltc1735-1 includes current foldback to help further limit load current when the output is shorted to ground. if the output falls by more than half, then the maximum sense voltage is progressively lowered from 75mv to 30mv. under short-circuit conditions with very low duty cycles, the ltc1735-1 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be conducting the peak current. the short- circuit ripple current is determined by the minimum on- time t on(min) of the ltc1735-1 (less than 200ns), the input voltage, and inductor value: d i l(sc) = t on(min) (v in /l) the resulting short circuit-current is: i mv r i sc sense lsc =+ 30 1 2 d () the current foldback function is always active and is not effected by the current latchoff function. fault conditions: output overvoltage protection (crowbar) the output overvoltage crowbar is designed to blow a system fuse in the input lead when the output of the regulator rises much higher than nominal levels. this condition causes huge currents to flow, much greater than in normal operation. this feature is designed to protect against a shorted top mosfet; it does not protect against a failure of the controller itself. the comparator (ov in the functional diagram) detects overvoltage faults greater than 7.5% above the nominal output voltage. when this condition is sensed the top mosfet is turned off and the bottom mosfet is forced on. the bottom mosfet remains on continuously for as long as the ov condition persists; if v out returns to a safe level, normal operation automatically resumes. note that dynamically changing the output voltage may cause over- voltage protection to be momentarily activated during output voltage decreases. this will not cause permanent latchoff nor will it disrupt the desired voltage change. with soft-latch overvoltage protection, dynamically chang- ing the output voltage is allowed and the overvoltage protection tracks the newly programmed output voltage, always protecting the load (cpu).
18 ltc1735-1 applicatio s i for atio wu u u minimum on-time considerations minimum on-time t on(min) is the smallest amount of time that the ltc1735-1 is capable of turning the top mosfet on and off again. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v vf on min out in () () < if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc1735-1 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc1735-1 in a properly configured application is less than 200ns. however, as the peak sense voltage decreases, the minimum on-time gradually increases as shown in figure 6. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with corre- spondingly larger current and voltage ripple. if an application can operate close to the minimum on- time limit, an inductor must be chosen that is low enough to provide sufficient ripple amplitude to meet the mini- mum on-time requirement. as a general rule keep the inductor ripple current equal or greater than 30% of i out(max) at v in(max) . pgood pin operation the pgood pin is a multifunction pin intended primarily to indicate when the output voltage is within 7.5% of its nominal set point. a window comparator monitors the v osense pin and activates an open-drain internal mosfet that pulls down the pgood pin when the output voltage is out of regulation. normally a 10k to 100k pull-up resistor is connected to this pin from a voltage source such as int vcc . do not apply a voltage greater than intv cc to this pin. dynamically changing the output voltage between two voltage levels greater that 7.5% apart from each other will invoke the power good indication, causing the pgood output to go low until the new output voltage is reached. when the dc voltage on the pgood pin drops below its 0.8v threshold, continuous mode operation is forced. in this case, the top and bottom mosfets continue to be driven synchronously regardless of the load on the main output. burst mode operation is disabled and current reversal is allowed in the inductor. this mode is forced whenever the output voltage is not within its 7.5% window. in addition to providing a power good output, the pgood pin provides a logic input to force continuous synchro- nous operation and allow synchronization to an external clock. the internal ltc1735-1 oscillator can be synchronized to an external oscillator by applying a clock signal to the pgood pin though a series resistor with a signal ampli- tude above 1.5v p-p . when synchronized to an external frequency, burst mode operation is disabled but cycle skipping is allowed at low load currents since current reversal is inhibited. the bottom gate will come on every 10 clock cycles to assure the bootstrap capacitor is kept refreshed. the rising edge of an external clock applied to the pgood pin starts a new cycle. if the output voltage is not within the 7.5% window around its nominal set point, the open-drain pgood output will pull low, disabling the external synchronization. the following table summarizes the possible states avail- able on the pgood pin. ? i l /i out(max) (%) 0 minimum on-time (ns) 100 150 40 1736-1 f06 50 0 10 20 30 250 200 figure 6. minimum on-time vs d i l
19 ltc1735-1 applicatio s i for atio wu u u table 1 pgood pin condition dc voltage: 0v to 0.7v no power good indication burst mode operation disabled/forced continuous current reversal enabled resistor pull-up to power good indication int vcc (or other dc burst mode, no current reversal voltage less than intv cc ) when power is good resistor to ext clock: no power good indication (0v to 1.5v) burst mode operation disabled no current reversal the circuit shown in figure 7 provides a power good output and forces continuous operation. transistor q1 keeps the voltage at the pgood pin below 0.8v thus disabling burst mode operation. when the window com- parator indicates the output voltage is not within its 7.5% window, the base of q1 is pulled to ground and the power good output appearing at the collector of q2 goes low. and control currents. v in current results in a small (< 0.1%) loss that increases with v in . 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom-side mosfets. by powering extv cc from an output-derived source (or other high efficiency source), the additional v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(efficiency). for example, in a 15v to 1.8v application, 10ma of intv cc current results in approximately 1.2ma of v in current. this reduces the midcurrent loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the mosfets, inductor and current shunt. in continuous mode, the average output current flows through l and r sense , but is chopped between the topside main mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 0.02 w , r l = 0.03 w , and r sense = 0.01 w , then the total resistance is 0.06 w . this results in losses ranging from 3% to 17% as the output current increases from 1a to 5a for a 1.8v output, or 4% to 20% for a 1.5v output. efficiency varies as the inverse square of v out for the same external components and power level. i 2 r losses cause the efficiency to drop at high output currents. 4. transition losses apply only to the topside mosfet(s), and only become significant when operating at high input voltages (typically 12v or greater). transition losses can be estimated from: transition loss = (1.7) v in 2 i o(max) c rss f figure 7. forced continuous operation with power good indication pin 4 pgood 470k q1 q2 100k 1735-1 f07 intv cc 10k power good efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1735-1 circuits: 1) ltc1735-1 v in current, 2) intv cc current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver
20 ltc1735-1 applicatio s i for atio wu u u other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and a very low esr at the switching frequency. a 25w supply will typically require a minimum of 20 m f to 40 m f of capacitance having a maximum of 0.01 w to 0.02 w of esr. other losses including schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load (esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1 m s to 10 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/ dc ratio cannot be used to determine phase margin. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. improve transient response and reduce output capacitance with active voltage positioning fast load transient response, limited board space and low cost are normal requirements of microprocessor power supplies. active voltage positioning improves transient response and reduces the output capacitance required to power a microprocessor where a typical load step can be from 0.2a to 15a in 100ns or 15a to 0.2a in 100ns. the voltage at the microprocessor must be held to about 0.1v of nominal in spite of these load current steps. since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. capacitor esr and esl primarily deter- mine the amount of droop or overshoot in the output voltage. normally, several capacitors in parallel are re- quired to meet microprocessor transient requirements. active voltage positioning is a form of deregulation. it sets the output voltage high for light loads and low for heavy loads. when load current suddenly increases, the output voltage starts from a level higher than nominal so the output voltage can droop more and stay within the specified voltage range. when load current suddenly
21 ltc1735-1 applicatio s i for atio wu u u decreases the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. less output capacitance is required when voltage positioning is used because more voltage variation is allowed on the output capacitors. active voltage positioning can be implemented using the opti-loop architecture of the ltc1735-1 and two resis- tors connected to the i th pin. an input voltage offset is introduced when the error amplifier has to drive a resistive load. this offset voltage is limited to 30mv at the input of the error amplifier. the resulting change in output voltage is the product of input offset voltage and the feedback voltage divider ratio. figure 8 shows a cpu-core-voltage regulator with active voltage positioning. resistors r1 and r5 force the input voltage offset that adjusts the output voltage according to the load current level. to select values for r1 and r5, first determine the amount of output deregulation allowed. the actual specification for a typical microprocessor allows the output to vary 0.112v. the ltc1735-1 reference accuracy is 1%. using 1% tolerance resistors, the total feedback divider accuracy is about 1% because both feedback resistors are close to the same value. the result- ing setpoint accuracy is 2% so the output transient voltage cannot exceed 0.082v. for v out = 1.5v, the maximum output voltage change controlled by the i th pin would be: d= = = v input offset voltage v v v v mv osense out ref .. . 003 15 08 56 with optimum resistor values at the i th pin, the output voltage will swing from 1.55v at minimum load to 1.44v at full load. at this output voltage, active voltage position- ing provides an additional 56mv to the allowable tran- sient voltage on the output capacitors, a 68% improvement over the 82mv allowed without active voltage positioning. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th pgood sense sense + v osense sgnd tg boost sw v in intv cc bg pgnd extv cc u1 ltc1735-1 c2 0.1 f c8 0.22 f c4 100pf c6 47pf c3 100pf r2 100k r1 27k pgood r6 0.003 gnd v out 1.5v 15a v in 7.5v to 24v gnd c5 1000pf c1 39pf + c10 4.7 f 10v c9 1 f c11 330pf c19 1 f + c15 to c18 180 f 4v c7 0.1 f q1 fds6680a q2, q3 fds6680a 2 c9, c19: taiyo yuden jmk107bj105 c10: kemet t494a475m010as c12 to c14: taiyo yuden gmk325f106 c15 to c18: panasonic eefue0g181r d1: central semi cmdsh-3 d2: motorola mbrs340 l1: panasonic etqp6f1r0sa q1 to q3: fairchild fds6680a r5: irc lrf2512-01-r003-j u1: linear technology ltc1735cs-1 1735-1 f08 d1 cmdsh-3 5v (optional) r7 10k r8 11.5k d2 mbrs340 c12 to c14 10 f 35v l1 1 h r5 100k r4 100k r3 680k figure 8. cpu-core-voltage regulator with active voltage positioning
22 ltc1735-1 applicatio s i for atio wu u u the next step is to calculate the i th pin voltage, v ith , scale factor. the v ith scale factor reflects the i th pin voltage required for a given load current in continuous inductor current operation. v ith controls the peak sense resistor voltage, which represents the dc output current plus one half of the peak-to-peak inductor current. the no load to full load v ith range is from 0.3v to 2.4v, which controls the sense resistor voltage from 0v to the d v sense(max) voltage of 75mv. for the circuit shown in figure 8, the calculated v ith scale factor is: v scale factor v range sense sistor value v vv v va ith ith sense max = d == re (. . ) . . ./ () 24 03 0003 0 075 0 084 assuming continuous inductor current, v ith is: vi i v scale factor v offset ith outdc l ith ith =+ d ? ? ? ? ? ? + 2 at full load current: va a va v v ith max pp () . / . . =+ ? ? ? ? ? ? + = - 15 5 2 0 084 0 3 177 at minimum load current: va a va v v ith min pp () ../. . =+ ? ? ? ? ? ? + = - 02 2 2 0 084 0 3 040 notice that d i l , the peak-to-peak inductor current, changes from light load to full load. increasing the dc inductor current decreases the permeability of the inductor core material, which decreases the inductance and increases d i l . the amount of inductance change is a function of the inductor design. if the circuit shown in figure 8 sustained continuous in- ductor current operation, the error amplifier would control v ith from 0.40v at light load to 1.77v at full load, a 1.37v change. during burst mode operation, the ltc1735-1 output voltage is controlled by a comparator, not the error amplifier. even though the error amplifier is not used in burst mode operation, it is necessary to assume linear operation for all error amplifier gain calculations. to create the 30mv input offset error, the voltage gain of the error amplifier must be limited. the desired gain is: a v input offset error v v v ith = d == 137 2003 22 8 . (. ) . connecting a resistor to the output of the transconductance error amplifier will limit the voltage gain. the value of this resistor is: r a error amplifier g ms k ith v m === 22 8 13 17 54 . . . to center the output voltage variation, v ith must be centered so that no i th pin current flows when the output voltage is nominal. v ith(nom) is the average voltage be- tween v ith at maximum output current and minimum output current: v vv v vv vv ith nom ith max ith min ith min () () () () .. .. =+ =+= 2 177 040 2 0 40 1 085 the thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor r5 that sources current into the i th pin and resistor r1 that sinks current to sgnd. to calculate the resistor values, first determine the ratio between them: k vv v vv v intvcc ith nom ith nom === .. . . () () 52 1085 1 085 379 v intvcc is equal to v extvcc or 5.2v if extv cc is not used. resistor r5 is: rk r k k ith 5 1 3 79 1 17 54 84 0 =+ = + = () (. ). .
23 ltc1735-1 applicatio s i for atio wu u u resistor r1 is: r kr k k k ith 1 1 3 79 1 17 54 379 22 17 = + = + = () (. ). . . unfortunately, pcb noise can add to the voltage developed across the sense resistor, r6, causing the i th pin voltage to be slightly higher than calculated for a given output current. the amount of noise is proportional to the output current level. this pcb noise does not present a serious problem but it does change the effective value of r6 so the calculated values of r1 and r5 may need to be adjusted to achieve the required results. since pcb noise is a function of the layout, it will be the same on all boards with the same layout. figures 9 and 10 show the transient response before and after active voltage positioning is implemented. notice that active voltage positioning reduced the transient re- sponse from almost 200mv p-p to a little over 100mv p-p . refer to design solutions 10 for more information about active voltage positioning. automotive considerations: plugging into the cigarette lighter as battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. but before you connect, be advised: you are plugging into the supply from hell. the main power line in an auto is the source of a number of nasty potential transients, including load dump, reverse battery and double battery. load dump is the result of a loose battery cable. when the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60v which takes several hundred milliseconds to decay. reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24v jump start cranks cold engines faster than 12v. the network shown in figure 11 is the most straight forward approach to protect a dc/dc converter from the ravages of an automotive power line. the series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. although the ltc1735-1 has a maximum input voltage of 36v, most applications will be limited to 30v by the mosfet bv dss . v in = 12v v out = 1.5v figure 8 circuit 1.582v 1.50v 1.418v 15a 0.2a 0a output voltage load current 50 m s/div 1735-1 f09 100mv/div figure 9. transient response without active voltage positioning v in = 12v v out = 1.5v figure 8 circuit 1.582v 1.50v 1.418v 15a 0.2a 0a output voltage load current 50 m s/div 1735-1 f10 100mv/div figure 10. transient response with active voltage positioning 5a/div 5a/div figure 11. plugging into the cigarette lighter v in 50a i pk rating 1735-1 f11 ltc1735-1 12v transient voltage suppressor general instrument 1.5ka24a
24 ltc1735-1 design example as a design example, assume v in = 12v (nominal), v in = 22v (max), v out = 1.5v, i max = 12a and f = 300khz, r sense and c osc can immediately be calculated: r sense = 50mv/12a = 0.042 w c osc = 1.61(10 7 )/(300khz) C 11pf = 43pf assume a 1.2 m h inductor and check the actual value of the ripple current. the following equation is used : d i v fl v v l out out in = ? ? ? ? ()( ) 1 the highest value of the ripple current occurs at the maximum input and output voltages: d i v khz h v v a l = m ? ? ? ? = 15 300 1 2 1 15 22 39 . (. ) . . the maximum ripple current is 32% of maximum output current, which is about right. next, verify the minimum on-time of 200ns is not violated. the minimum on-time occurs at maximum v in and mini- mum v out . t v vf v v khz ns on min out in max () () . () == = 15 22 300 227 the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fds6612a results in; r ds(on) = 0.03 w , c rss = 80pf. at maximum input voltage with t(estimated) = 50 c: p v v cc v a pf khz mw main = () + [] w () + ()()( )( ) = 15 22 12 1 0 005 50 25 0 03 1 7 22 12 80 300 568 2 2 . ( . )( ) . . because the duty cycle of the bottom mosfet is much greater than the top, two larger mosfets must be paral- leled. choosing fairchild fds6680a mosfets yields a parallel r ds(on) of 0.0065 w . the total power dissipation for both bottom mosfets, again assuming t = 50 c, is: p vv v a mw sync = ()() w () = 22 1 5 22 12 1 1 0 0065 959 2 . .. thanks to current foldback, the bottom mosfet dissipa- tion in short circuit will be less than under full-load conditions. c in is chosen for an rms current rating of at least 6a at temperature. c out is chosen with an esr of 0.01 w for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr ( d i l ) = 0.01 w (3.9a) = 39mv p-p since the output voltage is below 2.4v, the output resistive divider will need to be sized to not only set the output voltage but also to absorb the sense pins specified input current. r max k v vv k 124 08 24 15 21 3 () . .. . = ? ? ? ? = choosing 1% resistors: r1 = 21k and r2 = 18.7k yields an output voltage of 1.512v. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1735-1. these items are also illustrated graphically in the layout diagram of figure 12. check the following in your layout: 1. are the signal and power grounds segregated? the ltc1735-1 pgnd pin should tie to the ground plane close to the input capacitor(s). the sgnd pin should then connect to pgnd and all components that connect to sgnd should make a single-point tie to the sgnd pin. the synchronous mosfet source should connect to the input capacitor(s) ground. 2. does the v osense pin connect directly to the feedback resistors? the resistive divider r1, r2 must be con- nected between the (+) plate of c out and signal ground. the 47pf capacitor from v osense to sgnd should be as close as possible to the ltc1735-1. be careful locating the feedback resistors too far away from the applicatio s i for atio wu u u
25 ltc1735-1 applicatio s i for atio wu u u ltc1735-1. the v osense line should not be routed close to any other nodes with high slew rates. 3. are the sense + and sense C leads routed together with minimum pc trace spacing? the filter capacitor be- tween sense + and sense C should be as close as possible to the ltc1735-1. ensure accurate current sensing with kelvin connections to the sense resistors shown in figure 13. series resistance can be added to the sense lines to increase noise rejection. 4. does the (+) terminal of c in connect to the drain of the topside mosfet(s) as closely as possible? this capaci- tor provides the ac current to the mosfet(s). 5. is the intv cc decoupling capacitor connected closely between intv cc and the power ground pin? this capaci- tor carries the mosfet driver peak currents. an addi- tional 1 m f ceramic placed immediately next to the intv cc and pgnd pins can help improve noise performance. 6. keep the switching node (sw), top gate node (tg), and boost node (boost) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side (pins 9 to 16) of the ltc1735-1 and occupy minimum pc trace area. figure 13. kelvin sensing r sense figure 12. ltc1735-1 layout diagram + c out r1 r2 c b d b r sense d1 q2 + 4.7 f q1 + c in + l1 v in + v out 1735-1 f12 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c osc run/ss i th pgood sense sense + v osense sgnd tg boost sw v in intv cc bg pgnd extv cc ltc1735-1 47pf 1000pf c osc c c c ss intv cc c c2 r c sense + sense high current path 1735-1 f13 current sense resistor (r sense )
26 ltc1735-1 typical applicatio n s u 1.8v/5a converter with power good 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th pgood sense sense + v osense sgnd tg boost sw v in intv cc bg pgnd extv cc ltc1735-1 c ss 0.1 f c b 0.1 f c c2 220pf intv cc 1000pf 100k power good 47pf c c 470pf r c 33k r sense 0.01 v out 1.8v 5a c osc 43pf + 4.7 f + c out 150 f 6.3v 2 panasonic sp c in 22 f 50v cer q1 si4412dy q2 si4410dy c out : panasonic eefueog151r c in : marcon thcr70le1h226zt l1: panasonic etqp6f3r3hfa r sense : irc lr 2010-01-r010f 1735-1 ta02 d b cmdsh-3 r2 32.4k 1% r1 25.5k 1% mbrs140t3 v in 4.5v to 22v l1 3.3 h optional: connect to 5v sgnd cpu core voltage regulator for 2-step applications (v in = 5v) with burst mode operation disabled 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c osc run/ss i th pgood sense sense + v osense sgnd tg boost sw v in intv cc bg pgnd extv cc ltc1735-1 c ss 0.1 f c b 0.22 f c c2 220pf 47pf 100k 470k intv cc c c 220pf r c 20k 100k* *optional to defeat overcurrent latchoff r sense 0.004 v out 1.5v 12a 1000pf c osc 39pf + 4.7 f 1 f 100pf + c out 180 f 4v 3 c o 47 f 10v c in 150 f 6.3v 2 q1 fds6680a q2, q3 fds6680a 2 c out : panasonic eefueog181r c in : panasonic eefueoj151r c o : taiyo yuden lmk550bj476mm-b l1: coilcraft 1705022p-781hc q4, q5: 2n2222 r sense : irc lrf 2512-01-r004-j 1735-1 ta03 d b mbr0530 r2 32.4k 1% r1 25.5k 1% mbrd835l v in 5v l1 0.78 h v in 5v sgnd q4 q5 power good 10k
27 ltc1735-1 s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) package descriptio n u dimensions in inches (millimeters) unless otherwise noted. 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 s16 1098 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.009 (0.229) ref
28 ltc1735-1 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 1999 sn17351 17351fs lt/tp 0100 4k ? printed in usa typical applicatio u high efficiency dynamic output voltage selectable cpu power supply for speedstep enabled processors related parts part number description comments ltc1149 high efficiency synchronous step-down controller 100% dc, std threshold mosfets, v in < 48v ltc1159 high efficiency synchronous step-down controller 100% dc, logic level mosfets, v in < 40v lt1375/lt1376 1.5a 500khz step-down switching regulator high efficiency ltc1435a high efficiency low noise synchronous step-down controller, n-ch drive burst mode operation, 16-pin narrow so ltc1436a/ltc1436a-pll high efficiency low noise synchronous step-down converter, n-ch drive adaptive power tm mode 20-pin, 24-pin ssop ltc1474/ltc1475 ultralow quiescent current step-down monolithic switching regulator 100% dc, 8-pin msop, i q = 10 m a ltc1628 dual high efficiency 2-phase step-down controller antiphase drive, 28-pin ssop, 3.5v v in 36v ltc1702 550khz dual output synchronous step-down controller antiphase drive, 24-pin ssop, v in 7v ltc1709 polyphase tm synchronous controller with 5-bit vid up to 42a, minimum input capacitors, 1.3v v out 3.5v ltc1735 high efficiency synchronous step-down contoller, n-channel drive burst mode opertion, 16-pin narrow ssop ltc1736 high efficiency synchronous step-down controller with 5-bit vid control output fault protection, 24-pin ssop ltc1772 sot-23 high efficiency constant frequency step-down controller 100% dc, 550khz, sot-23, current mode adaptive power and polyphase are trademarks of linear technology corporation. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c osc run/ss i th pgood sense sense + v osense sgnd tg boost sw v in intv cc bg pgnd extv cc ltc1735-1 c s1 1000pf c c2 330pf c osc 47pf c1 47pf c c1 47pf c ss 0.1 f r c1 33k r7 100k r6 680k r8 4.7 jp1 latch-off disable pgood run intv cc + c2 4.7 f c4 1 f 5v input (optional) c2 47pf q4 2n7002 gnd c3 47pf r1 10k 0.5% v out 1.35v or 1.60v 12a v sel = 1: v out = 1.60v v sel = 0: v out = 1.35v d1 cmdsh-3 d2 mbrs340t3 c b 0.22 f q1 fds6680a c in 22 f 50v ceramic 2 l1 1.2 h r sense 0.004 v in 4.5v to 24v q2, q3 fds6680a 2 r5 10 1735-1 ta01 r3 33.2k 1% r2 14.3k 0.5% r4 10 + c out 180 f 4v sp 4 c f1 0.1 f c in : marcon thcr70e1h226zt c out : panasonic eefve06181r l1: panasonic etqp6f1r2hfa r sense : irc crf2512-01-r004f

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